CMOS technology is essential to the development of VLSI systems in today’s world. In deep submicron CMOS technology, power optimization has taken precedence over other considerations. The main issues resulting from the device’s shrinkage are power consumption reductions and overall chip power management. Optimization of power is a crucial for several designs in order to lower package costs and enhance battery life. Given that leakage accounts for a sizeable portion of the overall power dissipation of VLSI circuits, it is also a crucial factor in power optimization. The main aim of this research is to shed more detail on the advances and breakthroughs in the field of deep submicron CMOS circuit power optimization.