Designing effective adder circuits is crucial for contemporary extremely large-scale integration systems due to the growing demand for low-power and high-performance integrated circuits. To construct all kinds of processors and design different digital systems, full adders are essential. Data processing units (DPU), microcontrollers, microprocessors, and digital signal processors are among the devices that employ it. In this paper, a fully functional adder circuit based on CMOS transmission gates that has been tuned for excellent performance and low-power consumption is thoroughly examined. To design and simulate, the Xilinx Vivado tool is utilized to simulate the low-power, high-performance CMOS transmission gate-based complete adder circuit. The Cadence Virtuoso tool is used to evaluate the circuit's power consumption and delay. Compared to the conventional full adder, which has an energy consumption of 199.6 μW with a delay of 23.5 ns, the Transmission Gate Full Adder (TGFA) circuit had a lower area utilization and an energy consumption of 52.29 μW with a delay of 20.76 ns. When comparing these results, it is evident that the high-performance, energy-efficient full adder in the proposed system demonstrates superior effectiveness. Its design, which uses fewer MOS transistors, contributes to reduced power consumption and a notable speed improvement.