This paper presents efficient maximum and minimum computing architecture that can be used in Machine learning applications like the max pooling layer, SoftMax activation function, Morphological operations, etc. Proposed architecture is implemented using Verilog and tested using the vivado test bench. Design synthesis is performed using Cadence Genus, TSMC 90 nm technology node. The results show that the proposed Maximum computing architecture has achieved a 36.07% reduction in Area-Delay-Product (ADP) with a 7.63% increment in Power-Delay-Product (PDP), and the proposed minimum computing circuit has achieved a 45.09% reduction in ADP and a 26.52% reduction in PDP compared with (Zhang in Electronics (Switzerland) 10:10, 2021.). New algorithms for handling signed inputs are proposed. Pro-posed signed circuits have a slight increment in ADP and PDP compared to unsigned circuits, it is due to the extra circuit necessary to handle signed inputs.