Sorting is a fundamental operation in many computational fields, from image processing to scientific computing and wireless communication. As data volumes grow, traditional sorting algorithms often fall short in efficiency and resource management, especially when implemented in hardware for real-time applications. To address these challenges, efficient parallel sorting algorithms are essential for handling large-scale data processing tasks in a power and area efficient manner. This paper presents a new hybrid optimized bitonic sort algorithm, proposed by analyzing and comparing the results of odd–even sort, bitonic sort, and odd–even merge sort. Implemented in Verilog HDL, these designs are simulated in Cadence Incisive and synthesized in Genus. Key performance metrics, including the number of Compare-And-Swap (CAS) units, area (µm2), and power (mW), are examined. Results demonstrate that the optimized bitonic sort algorithm achieves improved power and area-efficiency by blending features from both bitonic sort and odd–even merge sort, particularly beneficial for small datasets.