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This research explores Binary Coded Decimal (BCD) Multiplication, addressing the need for high-speed arithmetic operations. A literature review identifies gaps in BCD multiplication based on Urdhva-Tiryakbhyam methods. Our methodology includes a detailed implementation of the Vedic BCD multiplier, showcasing efficiency gains. Results demonstrate accelerated processing, apt for digital signal processing and financial computations. Despite limitations, acknowledged advancements in VLSI open avenues for future research. The results presented in this paper shows improved performance in terms of delay and logic cell utilization.

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Design and Implementation of Vedic BCD Multiplier on Artix 7 FPGA Board

  • 会议论文

  • 发表日期：

    2025年

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  • Kanchan S. Tiwari,
  • Suraj Vijay Harale,
  • Fiza Yusuf Shaikh,
  • Yasin Badshah Shaikh

摘要

This research explores Binary Coded Decimal (BCD) Multiplication, addressing the need for high-speed arithmetic operations. A literature review identifies gaps in BCD multiplication based on Urdhva-Tiryakbhyam methods. Our methodology includes a detailed implementation of the Vedic BCD multiplier, showcasing efficiency gains. Results demonstrate accelerated processing, apt for digital signal processing and financial computations. Despite limitations, acknowledged advancements in VLSI open avenues for future research. The results presented in this paper shows improved performance in terms of delay and logic cell utilization.