Adder is a critical component of many digital systems and circuits, such as DSP processors, ALUs, and ASICs, that execute different various arithmetic operations. As the technologies scale down, the threshold voltage decreases, leading in increased power dissipation. This paper proposes a novel 14 T hybrid full adder and compares it with existing designs with respect to power usage, signal latency, and power delay product (PDP). Both the existing circuits and the proposed design are built and tested under identical conditions, utilizing 90 nm technology on Cadence Virtuoso. The comparison reveals that the proposed full adder improves the latency and PDP by 11.49% to 44.77% and 0.48% to 66.56%, respectively, hence making it appropriate for usage in speedy operations.