Verification of DDR4 SDRAM Using SystemVerilog
摘要
An essential part for any digital system is storage. The volatile storage necessitates significant effort in interface design and verification in data-access and preservation. The DDR4 SDRAM is the double-data-rate fourth-generation synchronous volatile dynamic random-access memory with the advantages of large capacity, high speed, low power consumption, and good stability. It is one of the prevalent variants, particularly in the application specific integrated circuits (ASIC) and server market. This work presents the verification of DDR4 SDRAM by elaborating its working in a complete verification environment. The extensive test cases provide a hand book to the verification engineers and building robust infrastructure. The verification of the DDR4 SDRAM is carried out for test conditions using write, read, and burst operations using effective verification environment. The structural and functional coverage of 83.3% provides a good start and further coverage obtained by direct test cases.