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This study provides a focused analysis on enhancing digital systems, particularly CORDIC algorithms and Wallace tree multipliers. CORDIC algorithms are widely used in signal and communication systems but suffer from high latency owing to unnecessary iterations. To address this, modified algorithms, such as CORDIC II and Radix-8 CORDIC, reduce iteration counts and improve speed using new angle sets and micro-rotation. Implemented on FPGA platforms, these designs minimize hardware resource usage. Additionally, integrating parallel prefix adders (PPAs) like Kogge-Stone, Han-Carlson, and Sklansky into Wallace trees optimizes multiplier performance, with Kogge-Stone achieving the fastest results despite higher power and area requirements. The key metrics, including hardware usage, precision, and accuracy, are presented in a comparative table.

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CORDIC Algorithm Implementation Using FPGA

  • 会议论文

  • 发表日期：

    2025年

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  • Kaushal Kulkarni,
  • Neha Joshi,
  • Isha Lale,
  • N. G. Nirmal

摘要

This study provides a focused analysis on enhancing digital systems, particularly CORDIC algorithms and Wallace tree multipliers. CORDIC algorithms are widely used in signal and communication systems but suffer from high latency owing to unnecessary iterations. To address this, modified algorithms, such as CORDIC II and Radix-8 CORDIC, reduce iteration counts and improve speed using new angle sets and micro-rotation. Implemented on FPGA platforms, these designs minimize hardware resource usage. Additionally, integrating parallel prefix adders (PPAs) like Kogge-Stone, Han-Carlson, and Sklansky into Wallace trees optimizes multiplier performance, with Kogge-Stone achieving the fastest results despite higher power and area requirements. The key metrics, including hardware usage, precision, and accuracy, are presented in a comparative table.