The era of quantum computing is a vast and growing field that applies to nanotechnology. With one-to-one mapping of the inputs and outputs, reversible gates don’t pursue any information loss fed to them. In the presented work, an optimized design of a 1-bit comparator is created using the Feynman gate and the Fredkin gate. Based on this design, a 64-bit reversible comparator with reduced quantum cost is designed with the addition of a BJN gate and a Peres gate. The resulting quantum cost of a single-bit, 4-bit, and 64-bit comparator is 12, 72, and 792, respectively. On the other hand, the garbage output count of the 64-bit comparator circuit is 394. The resulting design is efficient in terms of reduced quantum cost, fewer garbage outputs, and unity fanout. This research presents an innovative method for creating reversible comparator circuits for use in quantum computing applications. Optimizing comparator design is crucial for improving performance as the need for effective quantum algorithms increases. By building reversible comparators using Feynman and BJN gates, the technique lowers power consumption and increases speed. Analysis reveals that the proposed layout operates more efficiently and scalable than current techniques, underscoring its potential to enhance quantum computing capabilities.