This research presents a novel method for classifying digits using Convolutional Neural Networks (CNNs) on Field-Programmable Gate Arrays (FPGAs). The focus is on exploiting the parallel processing capabilities of FPGAs to achieve real-time digit recognition. The architecture incorporates optimization techniques, incorporating convolutional layers for efficient feature extraction, pooling layers for reducing dimensionality, and fully connected layers for accurate classification. The model is trained extensively on digit datasets to ensure its ability to generalize. In summary, the study introduces an innovative approach to real-time digit classification through the integration of CNNs on FPGAs, emphasizing optimization strategies and thorough training on digit datasets for robust performance. Experimental results demonstrate the proposed CNN’s efficacy, achieving high accuracy coupled with low-power consumption in digit classification. FPGA implementation enables parallel processing, substantially accelerating (Al Faruque et al. 2019) inference compared to software-based approaches. The abstract underscores resource utilization and power efficiency, showcasing the potential for expediting machine learning tasks in embedded environments. The study utilizes the xc7z010clg400-1 Zynq-7000, revealing that the LeNet-5 architecture achieves resource utilization of 8.99% of LUTs with a dynamic power consumption of 1.547W, indicating promising performance.