A novel Silicon carbide TMOS with integrated heterojunction diode is proposed and investigated to enhance high frequency and suppress switching oscillation in this article. The heterojunction diode formed by P-Poly/N-SiC is introduced as the freewheeling diode to replace the parasitic body pin diode of the SiC MOSFET, which improves the reverse recovery characteristics of the device. The proposed structure integrated HJD is surrounded by the P-base region and the P-shield of the MOS cells, to shield high electric fields and maintain a high breakdown voltage. In addition, heterojunction diodes do not have Schottky Barrier lowering effect and tunneling effects. As a result, the breakdown voltage is increased by 14% with the same specific on-resistance (Ron,sp) as ITS-MOS. The simulation results show that compared with traditional C-TMOS, the Miller capacitance (CGD) is reduced by 37.5%, the gate-drain charge (QGD) is reduced by 61.3%, the switching loss is reduced by 20%, and the reverse recovery charge is reduced by 20%.

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A Novel Integrated Heterojunction Diode SiC Trench MOSFET with Improved Switching and Reverse Recovery Performance

  • Xiaobo Cao,
  • Jing Liu,
  • Chuan Ma,
  • Shaowei Zhang,
  • Xiaoxing Fu,
  • Zhonggang Yin

摘要

A novel Silicon carbide TMOS with integrated heterojunction diode is proposed and investigated to enhance high frequency and suppress switching oscillation in this article. The heterojunction diode formed by P-Poly/N-SiC is introduced as the freewheeling diode to replace the parasitic body pin diode of the SiC MOSFET, which improves the reverse recovery characteristics of the device. The proposed structure integrated HJD is surrounded by the P-base region and the P-shield of the MOS cells, to shield high electric fields and maintain a high breakdown voltage. In addition, heterojunction diodes do not have Schottky Barrier lowering effect and tunneling effects. As a result, the breakdown voltage is increased by 14% with the same specific on-resistance (Ron,sp) as ITS-MOS. The simulation results show that compared with traditional C-TMOS, the Miller capacitance (CGD) is reduced by 37.5%, the gate-drain charge (QGD) is reduced by 61.3%, the switching loss is reduced by 20%, and the reverse recovery charge is reduced by 20%.