Scholarlink

Combining Si-IGBT and SiC-MOSFET in a hybrid parallel configuration integrates the lower conduction loss characteristics of Si-IGBT with the fast switching and lower losses of SiC-MOSFET. This hybrid approach offers significant advantages in improving the efficiency of power switching devices. However, the effects of different drive delays on switching losses between Si-IGBT and SiC-MOSFET are not well understood. Improper designing results in higher switching losses instead of lower switching losses, which can seriously affect the safety and reliability of the switching device. This work establishes a switching loss analysis model that takes into account the effects of drive delay. Simulation analysis of the switching losses in a hybrid parallel double-pulse circuit with different gate drive time delays for turn-on and turn-off was conducted to determine the optimal delay time for minimizing the switching losses. The simulation results show that under the proposed optimal delay timing, the turn-on losses are reduced by 32% and the turn-off losses are decreased by 67% with respect to the use of Si-IGBTs only.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Drive Delay Optimization for Mixed Parallel Switching Losses of Si-IGBT/SiC-MOSFET

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Yuan Shuaitao,
  • Gao Fanqiang,
  • Li Zixin,
  • Zhao Cong,
  • Zhang Ye,
  • Li Yaohua

摘要

Combining Si-IGBT and SiC-MOSFET in a hybrid parallel configuration integrates the lower conduction loss characteristics of Si-IGBT with the fast switching and lower losses of SiC-MOSFET. This hybrid approach offers significant advantages in improving the efficiency of power switching devices. However, the effects of different drive delays on switching losses between Si-IGBT and SiC-MOSFET are not well understood. Improper designing results in higher switching losses instead of lower switching losses, which can seriously affect the safety and reliability of the switching device. This work establishes a switching loss analysis model that takes into account the effects of drive delay. Simulation analysis of the switching losses in a hybrid parallel double-pulse circuit with different gate drive time delays for turn-on and turn-off was conducted to determine the optimal delay time for minimizing the switching losses. The simulation results show that under the proposed optimal delay timing, the turn-on losses are reduced by 32% and the turn-off losses are decreased by 67% with respect to the use of Si-IGBTs only.