Reversible logic has emerged as a profound research area in recent times, and contributed immensely to the development of the power efficient system design. The utilization of this technology extends across diverse other domains, like quantum computing, network security, and nanotechnology. This paper describes the design and analysis of Ripple Carry Adders (RCA). To implement the adders advanced reversible gates like Double Peres Gate (DPG) and TS Gates (TSG) are used. The analysis provides us with the fact that area utilization of the look up tables (LUT) and timing delay remains unchanged with the irreversible gates. The main advantages of the reversible logics are that they dissipate much lesser heat compared to the irreversible logics and also provides prevention of any data loss. It means that for the same design reversible logics are more beneficial. This paper consists of a comparative study of the LUT consumption and logic delay, along with that there are complete analysis of the parameters like GO (Garbage Output), QC (Quantum costs), and Gate count. All the results are obtained on Xilinx Vivado 18.2 software and the design was implemented on Basys3 FPGA board.