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The peculiarities of SAR ADC are low power consumption, energy-efficient architecture, aptness for fine CMOS processes, and extensive technology scaling. An 8-bit SAR ADC architecture with a dual-path bootstrapped switch and a triple-tail comparator is built with a sampling frequency of 1 MHz using 180 nm CMOS technology and a 1.8 V supply. At a signal frequency of 3.906 kHz, the power usage is 34.81 µW. It reaches dynamic characteristics with SNDR of 49.81 dB, SFDR of 60.42 dB, and ENOB of 7.98 bits, respectively. Additionally, it achieves static performance characteristics with 0.004 and 0.013 LSB for DNL and INL, respectively. In addition, the dynamic performance of corner analysis is investigated for a range of input frequencies up to the Nyquist rate.

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Design and Development of Power-Efficient SAR ADC with Dual-Path Switching and Triple-Tail Comparator for Biomedical Signal Processing

  • 会议论文

  • 发表日期：

    2025年

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  • Deepika Kumaradasan,
  • Sougata Kumar Kar,
  • Santanu Sarkar

摘要

The peculiarities of SAR ADC are low power consumption, energy-efficient architecture, aptness for fine CMOS processes, and extensive technology scaling. An 8-bit SAR ADC architecture with a dual-path bootstrapped switch and a triple-tail comparator is built with a sampling frequency of 1 MHz using 180 nm CMOS technology and a 1.8 V supply. At a signal frequency of 3.906 kHz, the power usage is 34.81 µW. It reaches dynamic characteristics with SNDR of 49.81 dB, SFDR of 60.42 dB, and ENOB of 7.98 bits, respectively. Additionally, it achieves static performance characteristics with 0.004 and 0.013 LSB for DNL and INL, respectively. In addition, the dynamic performance of corner analysis is investigated for a range of input frequencies up to the Nyquist rate.