As technology develops, neural networks (NNs) play a pivotal role in pattern recognition. This paper focuses on the implementation of a specialized NN for handwritten digit detection while emphasizing FPGA compatibility. It utilizes ZyNet for quantization and Verilog HDL code generation, the NN has achieved 97.11% accuracy on the MNIST digit training dataset and 96.69% on a hardware-specific MNIST test dataset. After efficient pre-processing of real-world handwritten images allows the network to recognize the images with an accuracy of 91.67%, demonstrating its potential for practical applications. Real-world handwritten image pre-processing involves binarization, standardization, and conversion to PNG format for optimal network analysis. This work paves the way for practical applications like real-time postal code recognition, embedded digit verification systems, bank check processing, etc. It also showcases the practical viability of FPGA-accelerated solutions, emphasizing the importance of quantization for hardware acceleration.

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Hardware-Specific Implementation of Neural Network for Handwritten Digit Detection

  • Ashwini Kumar Nayak,
  • Atin Mukherjee

摘要

As technology develops, neural networks (NNs) play a pivotal role in pattern recognition. This paper focuses on the implementation of a specialized NN for handwritten digit detection while emphasizing FPGA compatibility. It utilizes ZyNet for quantization and Verilog HDL code generation, the NN has achieved 97.11% accuracy on the MNIST digit training dataset and 96.69% on a hardware-specific MNIST test dataset. After efficient pre-processing of real-world handwritten images allows the network to recognize the images with an accuracy of 91.67%, demonstrating its potential for practical applications. Real-world handwritten image pre-processing involves binarization, standardization, and conversion to PNG format for optimal network analysis. This work paves the way for practical applications like real-time postal code recognition, embedded digit verification systems, bank check processing, etc. It also showcases the practical viability of FPGA-accelerated solutions, emphasizing the importance of quantization for hardware acceleration.