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The proposed model focuses on the design and performance enhancement of a 64-bit VMultiplier by utilizing the UTS, one of the 16 ancient sutras of VM. A modified architecture is proposed to achieve improved performance compared to a recent journal on 32-bit VMultiplier. Additionally, a 64-bit VMultiplier is designed according to the reference journal. The proposed 64-bit VMultiplier comprises three stages: the first stage consists of four 32-bit VMultipliers, the second stage incorporates a 96-bit CSA and a 95-bit modified CSKA, and internal stages include 8-bit and 16-bit Sklansky adders.

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MAC Design and Performance Improvement Using 64-Bit VMultiplier Based on UTS

  • 会议论文

  • 发表日期：

    2025年

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  • S. V. Sandeep,
  • S. Nischitha,
  • B. S. Balaji,
  • K. B. Naveen,
  • B. S. Raghu Kumar

摘要

The proposed model focuses on the design and performance enhancement of a 64-bit VMultiplier by utilizing the UTS, one of the 16 ancient sutras of VM. A modified architecture is proposed to achieve improved performance compared to a recent journal on 32-bit VMultiplier. Additionally, a 64-bit VMultiplier is designed according to the reference journal. The proposed 64-bit VMultiplier comprises three stages: the first stage consists of four 32-bit VMultipliers, the second stage incorporates a 96-bit CSA and a 95-bit modified CSKA, and internal stages include 8-bit and 16-bit Sklansky adders.