Multipliers are the basic building blocks of Digital Signal Processors (DSPs) and Vedic Multipliers are one of them. This paper deals with the design of 16-bit Vedic Multipliers that are implemented on an Artix-7 FPGA. For designing a Vedic Multiplier, three adders have been selected. The adders are first used individually and then by conceptualizing Hybrid Adders by combining any two or all the three of them distributed bit wise. This paper compares the performance of all the adders used for checking the reliability of the Multiplier design. Hybrid Adders show better performance than adders when used as individual while designing the multipliers.