The initial phase of the paper involved a comprehensive study of the types of LFSRs functionality, where the architecture and dataflow were thoroughly understood. Subsequently, a Verilog code implementing the required algorithm was meticulously written using a structural description approach. The accuracy of the codes was validated through Xilinx simulation, covering Galois LFSR, BS LFSR, and BS-SIC LFSR. Moving forward, hardware simulation was done on Spartan 6 FPGA board, yielding the desired results. Transitioning to the physical design and synthesis phase, the Verilog source code files (.vfiles) underwent elaboration in the Cadence backend. Waveform simulations were executed using the nclaunch tool within the Cadence software suite. The synthesis process was then initiated using the Genus tool in Cadence, resulting in the generation of comprehensive synthesis reports. The reports included essential parameter values such as area, power, and delay for all variants of LFSR in 45, 90, and 180 nm technology. Then, the reports were analyzed in-depth by comparing the results obtained with those of various technology nodes.