In energy-efficient digital circuits, reducing power consumption in fundamental arithmetic units is crucial. Adders are fundamental components in many computational circuits, adders are critical to the performance and energy efficiency of digital systems. Therefore, it is essential to develop adders that not only work faster but also minimize power consumption. This research provides valuable insights into the design of low-power arithmetic circuits, which are critical for energy-efficient computing applications. The work presents an in-depth analysis and implementation of low-power techniques on a 4-bit full adder constructed using a 1-bit full adder consisting of 28 transistors. Initially, a 28-transistor 1-bit adder is realized and then a 4-bit ripple carry adder (RCA). To reduce power dissipation, Low Control NMOS (LCNMOS) and Multi-Threshold CMOS (MTCMOS) logic were incorporated with both 1-bit and 4-bit RCA. The LCNMOS technique reduced the power by 36.19%, while the MTCMOS lowered the power by 79.2%. The results highlight the efficacy of these techniques in minimizing power consumption without compromising the functionality of the circuit. The schematics are realized in CMOS GPDK 90 nm CMOS technology in Cadence Virtuoso and Cadence Spectre for simulation and power analysis.