Transistors in microchips have been rapidly downscaled in the past fifty years, with tens of billions of them crammed into one microchip today, compared to the slightly above two thousand that fit into one chip in the early 1970s. This has caused drastic improvements in the power and efficiency of our electronic devices, positioning the semiconductor industry as one of the fastest-growing sectors globally. As nanowire dimensions continue to shrink, the design and fabrication of interconnects must also scale accordingly to maintain the desired performance and integration density. However, as they are downscaled, the size-dependent resistivity of metal interconnects presents a significant challenge, resulting in decreased conductivity and energy efficiency. This study explores the use of ruthenium as an interconnect, instead of the traditionally used copper, and examines its impact on the resistivity of nanowire samples. We make use of Transmission Electron Microscopy (TEM) to analyse the impact of annealing at 800 ℃ for varying durations and determine its impact on parameters such as linear grain size, grain area, and resistivity of nanowire samples. By identifying the more conductive metal for interconnects at smaller scales and determining the optimal duration for annealing, this project has laid the groundwork for future research in improving the efficiency of next-generation electronics.