This paper presents a hetero buried oxide (HBOX)—extended source (ES) tunnel FET architecture with a gate overlapping aimed at source region to decrease the ambipolar current and to elevate the on-state current. This structure also incorporates the extended source (ES) into the channel region so that it embodies both the point and line tunneling at the source-channel junction, thereby increasing the tunneling probability of the carriers from the source to channel region. In addition to the extended source (ES), the graded doping of drain region has also been done to reduce the ambipolar current in the vertical direction of the TFETs. Various electrical parameters of the device in particular on and off-states currents, Ion/Ioff ratio, and subthreshold slope (SS) have been analyzed by varying HBOX and silicon layer thickness. The high-K-BOX and low-K-BOX has been used at the source and at the drain sides, respectively. This has been done to boost the on-state current and to lower the ambipolar characteristics of the proposed tunnel FET. The characteristics of the proposed structure has been optimized concerning the physical dimension variation. The proposed structure provides SS of 15 mV/dec and an on/off current ratio of 1011. The steep subthreshold slope structure provides high switching speed and lends itself well to low-power applications. This device may also be appropriate for Analog/RF applications as it exhibits good capacitances, trans conductance and output conductance.