Approximate computing is a promising technique and a preferred approach to create streamlined, cost-effective, and high-speed solutions, especially in architectures that can accommodate certain levels of error tolerance. This approach strategically allows for the acceptance of minor errors or imprecisions in the computation, enabling significant reductions in both circuit area and power consumption without compromising the quality of results. It is applied in areas of image processing, digital signal processing (DSP), multimedia applications. Due to the phenomenon of persistence of vision, even slight introduction of errors in image processing applications often remain unnoticeable. In this study, we propose the utilization of an unsigned 8 × 8 Radix-8 Booth Multiplier for image processing applications, comprising of the units—Partial Product Generation Unit, Booth Encoding Unit, Booth Selection Unit, Partial Product Reordering Unit, and Adder Unit which consists of full adders and half adders. Our study introduces three distinct multiplier designs namely, AR8BM1, AR8BM2, and AR8BM3 each incorporating unique approaches, where AR8BM stands for Approximate Radix- 8 Booth Multiplier. AR8BM1 multiplier explores truncation within the PPRU unit. AR8BM2 multiplier extends this by incorporating truncation with carry compensation. AR8BM3 multiplier looks into the approximation of adders used in the adder unit. These approaches collectively aim to reduce area, power, and enhance efficiency while maintaining a considerable accuracy level. With respect to the exact Radix-8 Booth multiplier model, AR8BM1 showed a 12.87% improvement in area and a 25% reduction in power consumption. AR8BM2 displayed a 9.7% reduction in area and 14.27% power improvement. AR8BM3 demonstrates 10.75% area improvement and a 19.31% power reduction. The three proposed designs were tested for an image processing application.