Scholarlink

This paper delves into short-channel effects (SCEs) in a double-gate (DG) n-FinFET structure, assessing factors like source/drain gate length, oxide variations, and underlap configurations. Introducing underlap concepts showcases enhanced FinFETs performance, a breakthrough for nanoscale applications. These underlap configurations—Drain Underlap (DUL), Source Underlap (SUL), Both Source and Drain Underlap (BUL), and No Underlap (NUL)—represent innovative approaches to mitigate short-channel effects, improving control over the channel and reducing leakage. The utilization of a double-gate in FinFETs signifies precise control at a nanoscale level. By evaluating these configurations, the research provides insights crucial for advancing semiconductor technology, promising optimized performance, reduced power consumption, and heightened integration density in microchips. Ultimately, this work draws attention to novel strategies for improving transistor behavior and highlights the potential of double-gate FinFETs to push the boundaries of nanoscale applications within semiconductor devices. The reported short-channel effect parameters, notably a DIBL of 182 mV/V, SS of 74.4 mV/dec, and an Ion/Ioff ratio of 106, portray a highly promising scenario for RF analog applications.

错误：搜索内容不能为空，请输入英文关键词
错误：关键词超出字数限制，请精简
高级检索

Double-Gate Junction Underlap Dual Gate FinFET for RF and Analog Applications

  • 会议论文

  • 发表日期：

    2025年

查看全文
  • Manaswini Mishra,
  • Ananya Dastidar,
  • Raghunandan Swain

摘要

This paper delves into short-channel effects (SCEs) in a double-gate (DG) n-FinFET structure, assessing factors like source/drain gate length, oxide variations, and underlap configurations. Introducing underlap concepts showcases enhanced FinFETs performance, a breakthrough for nanoscale applications. These underlap configurations—Drain Underlap (DUL), Source Underlap (SUL), Both Source and Drain Underlap (BUL), and No Underlap (NUL)—represent innovative approaches to mitigate short-channel effects, improving control over the channel and reducing leakage. The utilization of a double-gate in FinFETs signifies precise control at a nanoscale level. By evaluating these configurations, the research provides insights crucial for advancing semiconductor technology, promising optimized performance, reduced power consumption, and heightened integration density in microchips. Ultimately, this work draws attention to novel strategies for improving transistor behavior and highlights the potential of double-gate FinFETs to push the boundaries of nanoscale applications within semiconductor devices. The reported short-channel effect parameters, notably a DIBL of 182 mV/V, SS of 74.4 mV/dec, and an Ion/Ioff ratio of 106, portray a highly promising scenario for RF analog applications.