This research focuses on the design, modeling and analysis of CMOS device architectures for integrated circuits designed for ultra-low power applications, particularly on the 35 nm CMOS technology node using the Synopsys TCAD tool. It is an experimental study of linear transfer characteristics, logarithmic curves, transconductance ( \(g_m\) ), output conductance ( \(g_o\) ) curves, current density, electrostatic potential and electric field. The main results show that reduction of channel length increases power efficiency without compromising device performance making these devices ideal for low power application. This research paper emphasizes the importance of CMOS technology in making efficient and high performing electronic devices. The study highlights advancements in electrical characteristics and device stability, offering insights for future innovations in CMOS technology.