Design and Implementation of Solar PV Fed Reduced Switch 63-Level Multilevel Inverter for Enhanced Power Quality
摘要
This paper deals with the design and execution of solar \(PV\) fed decreased switch \(63\) -level multilevel inverter for enhanced power quality. The proposed methodology aims to employ solar \(PV\) modules equipped with \(extreme value theorem\) ( \(EVT\) ) based \(MPPT\) technique as the voltage sources for the execution of 63–level multilevel inverter. In the reduced switch multilevel inverter topology, minimum numbers of switches are incorporated in the inverter to obtain the desired levels in staircase AC \(output voltage\) waveform. This concept serves two purposes: (i) it reduces the cost of the inverter as the minimum numbers of switches are utilized; (ii) it significantly increases the quantity of steps in the result voltage waveform with minimum increase in the components which lessens the \(THD\) notably. The decreased switch model of \(63\) -level inverter requires only nine switches and five sources for its implementation. The model of solar \(PV\) fed decreased switch \(63\) -level inverter has been simulated on the MATLAB platform and also experimentally validated. The performance of decreased switch MLI topology has been compared with customary MLI configurations on the basis of critical parameters. The superiority of decreased switch configuration over customary MLI topologies is established.