The current implementation of parametric array loudspeakers mainly divides into analog circuit and digital circuit implementations, and the digital circuit further divides into DSP and FPGA implementations. In the implementation of the parametric array loudspeaker, it is necessary to adopt an appropriate preprocessing method to ensure the low distortion of the demodulated difference frequency signal. Due to the complexity of the related preprocessing algorithms, the design of analog circuits is quite difficult. Debugging analog circuits is also inconvenient, which prolongs the development cycle. These problems restrict the development and application of parametric array loudspeakers. In recent years, with the development of digital signal processing and integrated technology, the functions of digital signal processors are becoming more and more powerful, and their basic signal processing algorithms are becoming mature. Parametric array loudspeaker systems based on DSP and FPGA can conveniently implement algorithm debugging and experimental research through software programming, making their design relatively simple. With the advancement of semiconductor technology, embedded processing chips such as FPGA not only have improved integration, but also have controlled costs. FPGA adopts parallel processing, which greatly reduces the delay of signal processing, thus having better real-time performance. In engineering implementation, a top-down design method is adopted. This design method has the following advantages. Starting from the functional description to the completion of physical implementation, it conforms to the design thinking of the designer. It is easy to change the design. The design cycle is shortened, and productivity is greatly improved. Therefore, the FPGA chip is one of the best choices for small batch systems to improve system integration and reliability. This chapter mainly implements the parametric array loudspeaker system based on the FPGA processor, which includes hardware and algorithm parts. The hardware part mainly includes the selection of chips, formulation of plans, and final implementation for four modules: power management circuits, Codec circuits, FPGA processor circuits, and D-class power amplifier circuits along with transducer matching circuits. The software part mainly includes the simulation and implementation of six modules: Codec chip control, serial-parallel conversion, carrier generation, voice activity detection, dynamic range control, and single sideband modulation. The algorithm was simulated through software, and based on this, various signal processing algorithms were implemented on the hardware platform using DSP Builder and Quartus II tools, and the resource consumption was evaluated. Finally, the performance indicators of the system were measured in the anechoic chamber.

FPGA Implementation of Parametric Array Loudspeakers

章节
发表日期：

2025年

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Jun Yang,
Peifeng Ji

摘要

The current implementation of parametric array loudspeakers mainly divides into analog circuit and digital circuit implementations, and the digital circuit further divides into DSP and FPGA implementations. In the implementation of the parametric array loudspeaker, it is necessary to adopt an appropriate preprocessing method to ensure the low distortion of the demodulated difference frequency signal. Due to the complexity of the related preprocessing algorithms, the design of analog circuits is quite difficult. Debugging analog circuits is also inconvenient, which prolongs the development cycle. These problems restrict the development and application of parametric array loudspeakers. In recent years, with the development of digital signal processing and integrated technology, the functions of digital signal processors are becoming more and more powerful, and their basic signal processing algorithms are becoming mature. Parametric array loudspeaker systems based on DSP and FPGA can conveniently implement algorithm debugging and experimental research through software programming, making their design relatively simple. With the advancement of semiconductor technology, embedded processing chips such as FPGA not only have improved integration, but also have controlled costs. FPGA adopts parallel processing, which greatly reduces the delay of signal processing, thus having better real-time performance. In engineering implementation, a top-down design method is adopted. This design method has the following advantages. Starting from the functional description to the completion of physical implementation, it conforms to the design thinking of the designer. It is easy to change the design. The design cycle is shortened, and productivity is greatly improved. Therefore, the FPGA chip is one of the best choices for small batch systems to improve system integration and reliability. This chapter mainly implements the parametric array loudspeaker system based on the FPGA processor, which includes hardware and algorithm parts. The hardware part mainly includes the selection of chips, formulation of plans, and final implementation for four modules: power management circuits, Codec circuits, FPGA processor circuits, and D-class power amplifier circuits along with transducer matching circuits. The software part mainly includes the simulation and implementation of six modules: Codec chip control, serial-parallel conversion, carrier generation, voice activity detection, dynamic range control, and single sideband modulation. The algorithm was simulated through software, and based on this, various signal processing algorithms were implemented on the hardware platform using DSP Builder and Quartus II tools, and the resource consumption was evaluated. Finally, the performance indicators of the system were measured in the anechoic chamber.