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This paper first designs two simulation testbench for airborne complex electronic verification project based on UVM (Universal Verification Methodology) framework. Second, detailed code implementation for reading and writing configuration table scenarios and the multi-channel gating scenarios is shown in this paper. Finally, this paper proposes a combination of formal and simulation methods to address the verification problem of complex code logic. The simulation results of the project indicate that the testbench proposed in this paper has a good integrity and can effectively detect logical conflicts in the design code.

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Simulation and Formalization Based Airborne Complex Electronic Verification Method and Implementation

  • 会议论文

  • 发表日期：

    2025年

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  • Yajun Gao,
  • Yiren Gao,
  • Qi Yang,
  • Xiaoxue Wu,
  • Wei Zheng

摘要

This paper first designs two simulation testbench for airborne complex electronic verification project based on UVM (Universal Verification Methodology) framework. Second, detailed code implementation for reading and writing configuration table scenarios and the multi-channel gating scenarios is shown in this paper. Finally, this paper proposes a combination of formal and simulation methods to address the verification problem of complex code logic. The simulation results of the project indicate that the testbench proposed in this paper has a good integrity and can effectively detect logical conflicts in the design code.