The MAGIC NOR gate-based memristor array is a promising processing-in-memory (PIM) approach due to its massive parallelism, flexible logical operation, and non-volatile memory characteristics. The V \(_{o}\) -V \(_{iso}\) MAGIC NOR gate operation mode is proposed to achieve high-throughput parallel computing and isolate other data within a memristor array. However, V \(_{iso}\) has a cumulative effect on the node voltage of the active row, calling into question the feasibility of V \(_{o}\) -V \(_{iso}\) operation mode. In this paper, circuit analysis defines the necessary circuit parameter conditions for enabling parallel computing and isolation units in the MAGIC NOR gate array. By algorithms in Python and CUDA C++ exploration, we determined that achieving the necessary conditions within the array parameters ranges—including the tolerance margin V \(_{\varDelta }\) , array size, V \(_{o}\) , V \(_{iso}\) and memristor parameters suitable for real-world circuit requirements—is unfeasible. In response to these challenges, we modified the memristor array architecture. The modified architecture employs transistors to activate compute units while safeguarding the rest selectively. The feasibility of this architecture is validated by SPICE with selected transistors fabricated using a 65 nm process, taking into account transistor resistance and the fluctuations in V \(_{set}\) and V \(_{reset}\) in the \(8\times 8\) modified memristor array. To accommodate the design requirement of the state-of-the-art memristor array, the feasibility of \(64\times 64\) modified memristor array, taking into account the impact of wire resistance, is further verified. This paper bridges the gap between reliable high-throughput parallel computing operation and MAGIC NOR PIM architecture.