In integrated circuit designs with multiple clock domains, the clock domain crossing (CDC) problem occurs when asynchronous signals are transmitted between domains due to differences in clock frequencies. This can lead to metastability and jeopardize circuit operation. Although integrated circuit design standards such as Do254 and Starc Verilog propose CDC constraints, manual detection is inefficient. To address this issue, this paper proposes a CDC static verification tool for RTL-based designs that incorporates synchronization patterns and clock domain checking. It analyzes netlists from the open-source Verilog synthesizer Yosys, extracts clock trees, and defines domains. By performing pattern matching, it identifies the use of synchronizers in the signal path, which is critical to reducing CDC problems. The tool’s functionality is demonstrated through comparative experiments and theoretical analysis using a typical Integrated Circuit (IC) design project. The verification results show that the tool can effectively identify typical CDC problems in the design and generate textual reports highlighting both synchronized and unsynchronized CDC paths, providing suggestions for improvement to assist IC designers in the early stages of design.