With the progressive rise of gallium nitride (GaN) materials, various new types of GaN-based devices have also become a research hotspot. FinFETs offer excellent gate control and performance but are complex, costly, and sensitive to poor interface quality as it triggers trap effects. Junctionless FinFETs simplify fabrication, reduce costs, and eliminate heterojunction parasitic effects. In the context of future device miniaturization, Junctionless FinFETs are poised to become highly promising due to their distinctive 3D fin channel conduction. Moreover, smaller fin dimensions are advantageous for optimizing their performance. This work builds on previous research by comparatively simulating the key parameters of Junctionless FinFETs, including the fin height, the distance between the drain and source, and the doping concentration of Si, using Silvaco TCAD. Simulation results show that in vertical devices, reasonable space restriction of 3D fin channels, like vertical nanosheet structures, can improve device performance.