Energy-efficient chips are of great significance for promoting energy conservation and emission reduction, building green electronic products, and promoting sustainable development and intelligent applications. The fundamental requirement of energy-efficient chip development lies in improving the energy efficiency of the overall chip by means of optimizing architectural design, using low-power design, implementing low-power physical implementation, and power management. The synthesis library subset screening technique is an optimization methodology for achieving energy-efficient design requirements by selecting appropriate library subsets during the logic synthesis phase. The standardized commercial cell libraries have demonstrated considerable potential and a wide range of standard cells. However, in the absence of guidance, it is difficult for the synthesizer to select the most appropriate subset of the synthesis library. To this end, this paper proposes a subset screening method for the synthesis library based on criteria cell factors, and systematically investigates the influence of the characteristics of the criteria cells in the synthesis libraries on the overall circuit properties. First, a criteria cell factor extractor is designed based on text processing and criteria cell simulation. Then, a synthesis library subset generator is constructed based on the criteria cell factor. The generated library subset is used for simulation to obtain circuit characteristics. Finally, a high-efficiency evaluation model is built based on the circuit characteristics. Based on simulation experiments with benchmark circuits, the results show that, without affecting circuit speed, by using the proposed synthesis library subset screening method, the benchmark circuits are able to obtain an average of 10% energy efficiency improvement during the synthesis process.