With the increasing demand for high-performance inverters, the influence of digital control delay cannot be ignored. Although several measures to reduce the influence of digital delay have been proposed, there is no suitable method to characterize the fractional sampling delay in the state-space model. Therefore, it is necessary to include the fractional sampling delay in the state-space model, which makes the system model more accurate when fractional sampling is employed to minimize the control delay. In this paper, a method of pole and zero placement with fractional control delay for LCL-Type Grid-Connected inverter is proposed. The state feedback control is designed by directly placing the pole and zero in the discrete-time domain. Meanwhile, the relationship between the position of zero and pole and the feedback coefficients of the state vectors is analyzed, and a complete design process is presented. An experiment is conducted to verify the feasibility of the model and the proposed design process.