In order to better understand how different full Adder designs affect computing accuracy and power efficiency, this study looks at them. Three different architectures of full adders are discussed: a traditional architecture with more transistors, a simplified “Sense Energy Recovery Full Adder” with less transistors and a novel “Transmission Gate Logic-based Full Adder” with fewer transistors. Different power efficiency trends are shown by simulations for different designs, suggesting possible trade-offs between transistor count and power usage. Furthermore, the implementation of the full adder, which is based on transmission gate logic, demonstrates encouraging power efficiency while building 4-to-2 compressors. These results demonstrate how low-power full adder topologies may improve energy-efficient digital system designs.