Network-on-Chip (NoC) is crucial for modern multicore systems, offering high throughput and low latency. However, its shared memory faces threats like illegal access and DDoS attacks. To enhance security, Memory Protection Units (MPUs) with permission tables are used to control access. NoC-MPU architecture uses TLBs and permission tables for request checks and domain isolation via CIDs, but this can cause high latency. To address this, DPU and NSM are combined for dynamic permission updates, though the tables remain static. Our paper introduces a novel Flexible and Efficient Real-Time Memory Protection Unit for NoC, featuring a hardware sandbox and taint-track monitor for pre-testing access requests. It supports dynamic memory region adjustments based on four permissions (RX, RWX, RW, R) and includes an access controller to counter DoS and side channel attacks. The design significantly boosts NoC security with minimal overheads: just 6.2% in throughput, 7.8% in area, and 4.8% in power, outperforming current solutions.

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SMP-NoC: A Flexible and Efficient Shared Memory Protection Unit on Network-on-Chip

  • Teng Wu,
  • Ying He,
  • Shengjun Wei,
  • Changzhen Hu

摘要

Network-on-Chip (NoC) is crucial for modern multicore systems, offering high throughput and low latency. However, its shared memory faces threats like illegal access and DDoS attacks. To enhance security, Memory Protection Units (MPUs) with permission tables are used to control access. NoC-MPU architecture uses TLBs and permission tables for request checks and domain isolation via CIDs, but this can cause high latency. To address this, DPU and NSM are combined for dynamic permission updates, though the tables remain static. Our paper introduces a novel Flexible and Efficient Real-Time Memory Protection Unit for NoC, featuring a hardware sandbox and taint-track monitor for pre-testing access requests. It supports dynamic memory region adjustments based on four permissions (RX, RWX, RW, R) and includes an access controller to counter DoS and side channel attacks. The design significantly boosts NoC security with minimal overheads: just 6.2% in throughput, 7.8% in area, and 4.8% in power, outperforming current solutions.