As performance demands continue to rise, shared-memory heterogeneous systems (SMHSs) have been widely adopted for their ability to enable efficient communication and data sharing between different heterogeneous cores. However, existing SMHS face challenges in uneven workload distribution among heterogeneous cores and suboptimal mapping schemes, preventing them from fully leveraging their architectural advantages. To address these issues, this paper introduces a performance model for SMHS named MAP-SIM. By performing performance modeling for CPUs and systolic array structures, and considering rational schemes for the partition and mapping of computational tasks, MAP-SIM aims to evaluate and optimize the computational performance of heterogeneous multicore architectures. The experimental results show that compared to previous schemes, MAP-SIM can lead to a 1.5 to 3.5 times increase in computational performance for SMHS.