The prominence in VLSI design has paradigm shift from high-speed circuit design to low power owing to the proliferation of portable electronic systems. Hither to the power optimization was focused on the internal core devices alone considering the logic design. But the overall power reduction depends on the logic family used to design the circuit, the topology, algorithm and architecture. In this context this research paper focuses on the optimization of leaf (primitive) cell to reduce power dissipation. This work vividly presents the design of low power Gate Diffusion Input Technique (GDI) XOR primitive cells for 90 nm CMOS ASIC library. The XOR gate is created using GDI MUX_F1, GDI MUX_OR and GDI MUX and combination of AND-NAND logic function of GDI logic. In this research work 3 different XOR gates are designed and their performances are observed with the existing counter-part in terms of logic technology like CMOS, PTL and TG. The simulation work and its performances are analyzed using Mentor graphics tool for 90 nm technology. The performance parameter observed are transistor utilized, power dissipation and product of power-delay (PDP). It is found that nearly 45% delay, 50 improvements in power and 25% improvement in transistor count.