Asynchronous FIFO (First in First out) plays an important role in data transfer between different clock domains, and it has also been increasingly widely used in radar and multi-machine processing system. This paper first introduces the characteristics of asynchronous FIFO and the difference between asynchronous FIFO and synchronous FIFO. Then the working mode of asynchronous FIFO is explained in detail and the method and advantages of converting binary code into Gray code and the possible problems of false empty and false full. And based on its characteristics, this paper mainly focuses on how to solve the problem of clock domain transformation in design process by using Gray code and how to judge FIFO state empty or full. At the end of the paper, according to the design idea, Verilog was used to write code and ModelSim was used to simulate individual signals, and some simulation results were analyzed and the future application of asynchronous FIFO was looked forward.