In the past, field-programmable gate arraysField-Programmable Gate Array (FPGA) (FPGAs) have had some notable successes when employed for Boolean and fixed-point genetic programming (GP) systems, but the more common floating-point representations were largely off limits, due to a general lack of efficient device support. However, recent work suggests that for both the training and inference phases of floating-point-based GPFloating-point-based GP, contemporary FPGAField-Programmable Gate Array (FPGA) technologies may enable significant performance and energy improvements—potentially multiple orders of magnitude—when compared to general-purpose CPU/GPU devices. In this chapter, we highlight the potential advantages and challenges of using FPGAsField-Programmable Gate Array (FPGA) for GP systems, and we showcase how novel algorithmic considerations likely need to be made in order to extract the most benefits from specialized hardware. Primarily, we consider tree-based GP, although we include suggestions for other program representations. Overall, we conclude that the GP community should earnestly revisit the use of FPGAField-Programmable Gate Array (FPGA) devices, especially the tailoring of state-of-the-art algorithms to FPGAs, since valuable enhancements may be realized. Most notably, FPGAsField-Programmable Gate Array (FPGA) may allow for faster and/or less costly GP runs, in which case it may also be possible for better solutions to be found when allowing an FPGAField-Programmable Gate Array (FPGA) toDigital design consume the same amount of runtime/energy as another platformHardware/software co-design.

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It’s Time to Revisit the Use of FPGAs for Genetic Programming

  • Christopher Crary,
  • Greg Stitt,
  • Bogdan Burlacu,
  • Wolfgang Banzhaf

摘要

In the past, field-programmable gate arraysField-Programmable Gate Array (FPGA) (FPGAs) have had some notable successes when employed for Boolean and fixed-point genetic programming (GP) systems, but the more common floating-point representations were largely off limits, due to a general lack of efficient device support. However, recent work suggests that for both the training and inference phases of floating-point-based GPFloating-point-based GP, contemporary FPGAField-Programmable Gate Array (FPGA) technologies may enable significant performance and energy improvements—potentially multiple orders of magnitude—when compared to general-purpose CPU/GPU devices. In this chapter, we highlight the potential advantages and challenges of using FPGAsField-Programmable Gate Array (FPGA) for GP systems, and we showcase how novel algorithmic considerations likely need to be made in order to extract the most benefits from specialized hardware. Primarily, we consider tree-based GP, although we include suggestions for other program representations. Overall, we conclude that the GP community should earnestly revisit the use of FPGAField-Programmable Gate Array (FPGA) devices, especially the tailoring of state-of-the-art algorithms to FPGAs, since valuable enhancements may be realized. Most notably, FPGAsField-Programmable Gate Array (FPGA) may allow for faster and/or less costly GP runs, in which case it may also be possible for better solutions to be found when allowing an FPGAField-Programmable Gate Array (FPGA) toDigital design consume the same amount of runtime/energy as another platformHardware/software co-design.