YANA: Bridging the Neuromorphic Simulation-to-Hardware Gap

Spiking Neural Networks (SNNs) promise significant advantages over conventional Artificial Neural Networks (ANNs) for applications requiring real-time processing of temporally sparse data streams under strict power constraints – a concept known as the Neuromorphic Advantage. However, the limited availability of neuromorphic hardware creates a simulation-to-hardware gap that impedes algorithmic innovation, hardware-software co-design, and advancement of mature open-source ecosystems. To bridge this gap, we introduce Yet Another Neuromorphic Accelerator (YANA), an accessible FPGA-based digital SNN accelerator that is supported by an easy-to-use software framework for neuromorphic application development. YANA implements a five-stage, event-driven processing pipeline that fully exploits temporal and spatial sparsity while supporting arbitrary SNN topologies through point-to-point neuron connections. Its software framework integrates seamlessly with popular open-source tools to provide a complete stack for the development and deployment of neuromorphic algorithms targeting YANA. We demonstrate that inference latency on YANA scales near-linearly with both spatial and temporal sparsity levels through experiments with the Spiking Heidelberg Digits dataset, achieving real-time acceleration factors of approximately 30x to 3000x. In the FPGA, a single YANA core that supports up to \(2^{17}\) synapses and \(2^{10}\) neurons utilizes 740 LUTs, 918 registers, 2 DSPs and 7.2 Mbit of on-chip memory. YANA provides a public, event-driven platform designed to exploit sparsity, while its integration with open-source tools creates a complete neuromorphic development stack. This represents an important milestone in making neuromorphic hardware more accessible and in fostering innovation.