A Method for Solving Abnormal Reset Issues in Digital Signal Processors

Digital Signal Processors (DSPs) are widely used in embedded systems. However, under extreme environmental conditions such as high/low temperatures and electromagnetic interference, DSP modules frequently experience abnormal resets, compromising system stability and safety. Existing research predominantly focuses on single-factor solutions, lacking in-depth exploration of hardware-software co-design. This study employs Fault Tree Analysis (FTA) [1] to systematically identify root causes of DSP module resets. By analyzing hardware interfaces and software design issues, we propose a co-design optimization approach, including interrupt service routine (ISR) optimization, invalid interrupt masking, and level-shifting interface improvements. Experimental results demonstrate that the improved DSP module achieved zero reset faults during 100-h operation in a − 55 °C to 70 °C temperature-controlled environment. Compared to the original system (1.5 resets per temperature cycle), the reset rate dropped to zero. Our hardware-software co-design effectively resolves abnormal resets in extreme environments, offering a novel technical pathway for enhancing embedded system reliability.