In view of the problem that the existing detection models are bulky and lead to difficulties in deploying at edge devices, this paper proposes a novel lightweight PCB small target defect detection algorithm based on YOLOv8n, named NLW-YOLOv8n. First, the FasterNet Block structure is employed to optimize the C2f module in the backbone network, reducing redundant computations and memory access, thereby mitigating the issue of model size inflation caused by feature redundancy. Second, the Squeeze-and-Excitation (SE) channel attention mechanism is introduced to enhance the network’s representational capacity. Concurrently, a ConvMLP Block structure is constructed to improve the C2f module in the Neck section, enhancing detection performance while further reducing model complexity. Finally, an improved WIoU loss function is adopted to further boost detection accuracy. Experimental results demonstrate that, compared to the original YOLOv8n algorithm, the proposed method increases Recall by 0.9%, reduces model weight size by 15.4%, decreases the number of parameters by 16.2%, and reduces computational complexity by 16.0%. In comparison with existing detection models, NLW-YOLOv8n not only maintains detection accuracy and improves recall to reduce missed detections, but also achieves significant progress in model lightweighting, providing strong support for deployment on edge devices.