Design, Control, and Analysis of Discrete Frequency Locked Loop for DSTATCOM with Optimized PI Gains

This article involves the utilization of three-phase three-wire Distribution Static Compensator (DSTATCOM) as a compensating device to mitigate the current related power quality issues caused by the nonlinearity and unbalanced condition of the load. Control circuit of this system includes discrete frequency locked loop (DFLL) to estimate the fundamental grid parameters. The control technique generates the fundamental frequency component from the frequency value of an applied periodic signal which largely functions in continuous-time domain which is discretized by utilizing the appropriate value of the sampling frequency through which the capability of harmonic filtration is formed. The discrete second-order harmonic oscillator is operated with the help of orthogonal vectors \(\alpha -\beta\) in stationary reference frame. It omits the utilization of the d-q reference frame which results in faster computation with accuracy. The efficient tuning of the PI gains necessary for generating the gate pulse for the voltage source converter is obtained by implementing the Whale Optimization Algorithm due to it structural form which retains the global value. It optimizes the DC link voltage and keeps the settling time, rise time, and peak overshoot to minimum when compared to manual method of obtaining the PI gains. The effectiveness of the control algorithm is validated through the MATLAB simulation results in Power Factor Correction (PFC) and Zero Voltage Regulation (ZVR) mode. The experimental results are obtained through hardware development which further strengthened the efficacy of the control algorithm.