The floating-point multiplier is an important coprocessor component of modern microprocessors and is the core of real-time image processing and deep learning computing. Compared to fixed-point multipliers, the dynamic range is wider, but the complexity is higher. With the rapid development of autonomous driving, artificial intelligence and the Internet of Things, the massive data and complex calculations required for these applications put forward high requirements for the design of the operation unit circuit, in which the multiplier consumes more resources and becomes the bottleneck of the operation unit design. This makes high-efficiency and low-power multipliers the focus of circuit design in recent years. High performance and low power consumption have become the trend in combined cell circuit design for edge computing applications. In this paper, an effective half-precision approximate floating point multiplier design for edge computing (MP4-App-Mul) is proposed. The architecture is based on shift-add approximation (SSA) and sparse processing to optimize power consumption and performance. Compared with the exact multiplier, the proposed approximate multiplier (MP4-App-Mul) has significant advantages in hardware performance, with 86.5% reduction in power and 58.4% reduction in area. Compared with similar multipliers, it achieves better comprehensive performance in accuracy, area, and power consumption. The new approximate multiplier is applied to image processing and neural network applications. Evaluations show that the new unit performs well in various tests: its image processing effect is equivalent to the exact multiplier; in deep learning tests, it excels in accuracy across models, with high adaptability and good accuracy for various neural network models. Meanwhile, in hardware performance, the new structure achieves significant optimization in key indicators such as area, power consumption, and latency.