Deeply fused many-core (DFMC) for high performance computing systems has achieved significant success over the past decade. However, there has been a lack of architecture simulators to assist in analyzing the impact of different configurations on application performance with DFMC. This study implemented a simulator named HManyCore-Sim for a new generation of Sunway many-core processor using dual simulation engines and parent-child process co-simulation mechanism. HManyCore-Sim implements detailed simulations of certain key component such as multi-level storage hierarchy simulation, including local memory (LDM), continuous shared memory, IO register space, DCache, ICache etc. HManyCore-Sim also implements specialized network-on-chip (NoC) simulation which enables Direct Memory Access (DMA) and Remote Memory Access (RMA) testing to approach actual chips, with a minimal mean absolute error (MAE) is 2%, and the Pearson correlation coefficient is above 99%. We overcome the difficulty of sampling DFMC programs and realize the sampling acceleration simulation technology based on heterogeneous instruction traces.