In-memory computing performs calculations in place where data is stored, eliminating the bandwidth limitations of the traditional von Neumann architecture. Existing methods have applied it to convolution calculations, but they fail to fully exploit the parallelism of the array, resulting in low throughput. We propose HT-DLC, a data layout and computing design for logic-in-memory convolution. We consider the data-dependent characteristics of the multiply-accumulate (MAC) operations that constitute the convolutional layer. By storing the data required by a MAC in a single row of the array to reduce inter-row replication, we maximize the parallelism of the array. And we consider the case of storing multiple MACs in a single array row and design a method for selecting input data of MAC to improve area utilization. When performing convolution on grayscale images using convolutional kernels of different widths, compared to stateful logic image processing accelerator based on the state-of-the-art synthesis flow STAR, our implementation of image convolution achieves an average throughput improvement of 15.11 \(\times \) and an average reduction of 93.11% in the computational delay of a single MAC, while the area utilization is reduced by an average of 7.28%. The results show that using HT-DLC for convolution can fully exploit the parallelism of the array, resulting in higher execution efficiency and lower average delay per MAC.