Systolic array accelerators have emerged as a mainstream architecture for deep neural networks (DNNs) owing to their efficient dataflow and high parallelism. Mapping strategies determine how computations and data transfers are orchestrated, and thus have a critical impact on accelerator performance. Comprehensively representing feasible mapping strategies (i.e., the mapping space) and efficiently evaluating their performance are essential for fully exploiting accelerator capabilities. However, existing methods inadequately model the data path from off-chip memory to processing elements (PEs) in systolic arrays, leading to suboptimal mapping strategies and degraded performance. Additionally, under constrained buffer capacities, conventional loop-nest scheduling provides insufficient temporal locality for effective on-chip data reuse. Moreover, previous performance models struggle to balance simulation accuracy with efficiency. To overcome these limitations, we propose a novel mapping strategy optimization framework for systolic array accelerators, introducing three key innovations: (1) fine-grained tiling and 6D loop-nest scheduling strategy to capture data movement from off-chip memory to the systolic array, enabling full data path modeling and better utilization of on-chip resources; (2) loop reversal optimization to prioritize computations on buffered data across iterations, enhancing temporal locality and on-chip data reuse; and (3) an event-driven performance model advancing simulations only at critical scheduling and dependency events, achieving high accuracy with significant efficiency gains. Experimental results demonstrate that our framework reduces latency by up to 37.63% and lowers energy consumption by up to 19.97% compared to the state-of-the-art FAMS framework. In addition, our performance model achieves an average \(38.3\times \) speedup in mapping strategy evaluation.