Combinatorial optimization problems (COPs) hold significant application value in logistics, chip design, resource allocation and so on. Ising machines demonstrate unique advantages in solving COPs through physical annealing processes. However, existing Ising architectures face two key challenges: first, current annealing strategies struggle to balance parallelism and solution quality, with existing parallel annealing methods often trapped in local optima while conventional serial methods exhibit prohibitively slow convergence; second, the hardware overhead of spin update circuits scales linearly with spin count, resulting in low spin integration density. To address these challenges, we propose three key innovations: a novel Dynamic-ratio Parallel Annealing (DPA) strategy that dynamically adjusts spin flip ratios during the annealing process while preserving solution quality and significantly improving convergence speed, an approximate computing approach using 8-bit segmented adders that maintains computational accuracy while significantly reducing hardware complexity, and a hardware-optimized hard- \(\sigma \) method that further simplifies probability flip calculations by replacing exponential operations with addition-based approximations. Comprehensive evaluations show Approximate Computing based Ising Machine with Dynamic-ratio Parallel Annealing (ACIM) achieves 10–100 \(\times \) faster convergence than baseline approaches with only 0.54% accuracy loss. The implementation achieves a 40.03% area reduction in the adder circuits used for spin state updates.