Traditional audio processing systems are constrained by the challenges of high power consumption and high latency. To address these challenges, this paper proposes SpikeEAR, an end-to-end spiking auditory system that implements a Sensing-Computing Integration architecture on a single FPGA. SpikeEAR achieves ultra-low end-to-end latency by seamlessly integrating a biomimetic cochlea, utilizing a novel noniterative adaptive encoding scheme, with a deeply pipelined Spiking Neural Network (SNN) accelerator. We implement the system on a Xilinx Zynq platform to evaluate the latency and power consumption. SpikeEAR achieves a 95.69 % recognition accuracy on a subset of the Google Speech Commands dataset, with an end-to-end latency of only 256.95  \(\upmu \) s. This latency represents a \(4\sim 7 \times \) improvement over recent FPGA-based solutions. This high-performance operation is achieved within a total power budget of 1.25 W. The overall performance validates the SCI architecture as a superior approach for constructing high-performance, low-power intelligent auditory systems for edge devices.

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SpikeEAR: Low-Power Neuromorphic Auditory System for Real-Time Scene Analysis on FPGA

  • Yiwei Si,
  • Hao Yu,
  • Yuhang Zhu,
  • Sizhao Li,
  • Zechao Liu,
  • Yongrui Zhang,
  • Di Gao

摘要

Traditional audio processing systems are constrained by the challenges of high power consumption and high latency. To address these challenges, this paper proposes SpikeEAR, an end-to-end spiking auditory system that implements a Sensing-Computing Integration architecture on a single FPGA. SpikeEAR achieves ultra-low end-to-end latency by seamlessly integrating a biomimetic cochlea, utilizing a novel noniterative adaptive encoding scheme, with a deeply pipelined Spiking Neural Network (SNN) accelerator. We implement the system on a Xilinx Zynq platform to evaluate the latency and power consumption. SpikeEAR achieves a 95.69 % recognition accuracy on a subset of the Google Speech Commands dataset, with an end-to-end latency of only 256.95  \(\upmu \) s. This latency represents a \(4\sim 7 \times \) improvement over recent FPGA-based solutions. This high-performance operation is achieved within a total power budget of 1.25 W. The overall performance validates the SCI architecture as a superior approach for constructing high-performance, low-power intelligent auditory systems for edge devices.