SD-YOLO: A Lightweight and Real-Time Model for Chip Surface Defect Detection

Addressing the challenges posed by small defect target sizes, complex surface textures, stringent real-time demands of industrial production lines, and constrained computing resources on edge devices in chip surface defect detection, We introduce SD-YOLO, a method for detecting defects on chip surfaces, derived from the YOLO11n architecture. To address the issues of excessive parameters and computational demands inherent in the original YOLO11n backbone network, we designed a ShuffleNet-based Dilated Convolutional Network module to replace the original backbone. This module reduces model parameters by optimizing channels and adjusting the parameters of grouped convolution, while simultaneously ensuring effective extraction of defect feature details. Additionally, to tackle the inadequate integration of defect features across multiple scales and the elevated computational cost associated with traditional feature fusion modules, we introduce a Defect-aware Channel and Spatial Re-calibration and Fusion module. This module improves the interplay between surface texture attributes and deep semantic characteristics without adding to the inference time. The model was trained using a self-constructed chip surface defect dataset from the Tsinghua University. The SD-YOLO model attains a mean Average Precision of 98.1%, a 2.5% improvement relative to the baseline YOLO11n. Concurrently, the detection speed is significantly increased, reaching 285.7 FPS, representing a 31.4% acceleration Contrast to the original model. Furthermore, the parametric efficiency is also improved, with the model size reduced by 16.6 M parameters to a total of 9.2 M. These results indicate that the proposed method effectively meets the requirements to achieve accurate and timely results in identifying flaws on industrial chip surfaces.