The emergence of CPU-GPU integrated System-on-Chip architectures like Apple’s M1 has made Unified Memory Architecture mainstream in computing. While UMA eliminated the CPU-GPU data copy overhead that was a major bottleneck in traditional dGPU systems, it shifted the optimization focus to kernel-internal memory access patterns. This paper analyzes how memory optimization strategies based on data access patterns affect cryptographic algorithm performance in SoC environments. We implemented the block cipher ARIA in Counter (CTR) mode on Apple M1 GPU using the Metal framework, designing six implementation configurations that systematically vary the storage locations of ARIA’s primary data structures—S-boxes and round keys—across device, threadgroup, and constant memory spaces. Experimental results confirmed that memory strategies optimized for data access patterns have a decisive impact on performance. A hybrid strategy placing S-boxes with irregular access patterns in threadgroup memory and round keys with uniform broadcast access patterns in constant memory achieved 451.93 MB/s throughput, representing 47.07% improvement over the baseline configuration. These findings demonstrate that precisely analyzing data access patterns and utilizing appropriate memory hierarchies remains key for maximizing GPU kernel performance even in UMA environments.